1. Field of Invention
The present invention relates to an analog-to-digital converter. More particularly, the present invention relates to a flash analog-to-digital converter.
2. Description of Related Art
FIG. 1 shows the basic structure of a conventional flash analog-to-digital converter (ADC). The conventional flash ADC operates by comparing an analog input signal Vin with reference voltages by using multiple comparators 110, then synthesizing the compared results to output an N-bit digital output signal Vout by using a thermometer code encoder 120. The reference voltage of each comparator is obtained by dividing a reference voltage (between Vref+ and Vref−) using series resistors.
Specifically, an N-bit ADC needs 2n resistors and 2n−1 comparators, and the reference voltage (between Vref+ and Vref−) can be divided to 2n different reference voltages by 2n resistors so as to allow the analog input signal Vin to be compared with the reference voltages.
Each of the comparators generates a digital output voltage representing the logic “1” when the analog input signal is higher than the reference voltage. In contrast, each of the comparators generates a digital output voltage representing the logic “0” when the analog input signal is lower than the reference voltage. These 1s and 0s are referred to as thermometer codes. The 2n−1 thermometer codes are synthesized as an N-bit digital output signal by the thermometer code encoder.
As shown in FIG. 1, since the flash ADC does not need sample-and-hold circuits, a data output can be generated in every clock pulse. As a result, the flash ADC can easily achieve high speed conversion performance, and thus is frequently used in medium- and low-resolution applications, as well as high-speed applications. In particular, flash ADCs are used in hard disks, read/write interfaces of CD-ROM drives, and high speed receivers. However, the flash ADC needs many comparators (for example, an N-bit ADC needs 2n−1 comparators), and thus difficulties are encountered with respect to promoting resolution performance.
A comparator of the conventional flash ADC is shown in FIG. 2. With reference to FIG. 2, one comparator requires seven NMOSs (n-type metal-oxide-semiconductors) N1-N7 and seven PMOSs (p-type metal oxide semiconductors) P1-P7, that is, 14 transistors in total. Thus, this configuration not only increases the chip area but also increases power consumption.
If the conventional comparator in FIG. 2 is used, each comparator requires 14 transistors, and the N-bit flash ADC requires 14×(2n−1) transistors in total. Thus, a typical 6-bit ADC requires 882 transistors while a typical 16-bit ADC requires almost one million transistors. In other words, if it is desired to increase the resolution of an ADC, quite a large circuit layout area is needed and a significant amount of power consumption will be involved. However, the cost of a chip escalates with an increased circuit layout area, and the increased power consumption results in unnecessary heat generation.
In view of the above, a traditional flash ADC with high resolution requires many comparators, and thus is associated with a huge layout area and high power consumption. Further, the precision of the traditional flash ADC is limited by the poor matching among the elements thereof.
Hence, a flash ADC that provides high speed and high resolution with to fewer transistors would be the optimum solution in the area of ADC technology, resulting in reduced circuit layout area, less power consumption, and lower cost.